Shallow trench isolation (STI) is widely used as an isolation technique in semiconductor devices. The STI technique is such as to form a trench in a silicon substrate, filling the trench with an oxide layer and planarizing the oxide layer, to form an isolation layer. Since a trench isolation layer exhibits good isolation characteristic and is narrow in occupancy area, it can properly meet the tendency that the integration density of a semiconductor device is increasing.
However, in the trench isolation layer, a dishing failure occurs depending on a difference in the area of the isolation layer during planarization. FIG. 1 is a sectional view illustrating an example of such a failure.
As illustrated in FIG. 1, after a trench 11 is formed in a field region of a silicon substrate 10, an oxide layer 12 is deposited so as to fill the trench 11. A chemical mechanical polishing (CMP) process is performed to planarize the oxide layer 12. The extent of the planarization of the oxide layer 12 varies depending on the difference in the area of the isolation layer, that is, depending on whether the area of the trench 11 is wide or narrow. In other words, the so-called dishing failure, i.e., the phenomenon wherein a middle portion of the oxide layer 12 is depressed, occurs in the trench 11 having a relatively big area. This dishing failure can causes a defect in a semiconductor device during a subsequent process.
To prevent the failure during the planarization process and to maintain a uniform thickness and profile of an isolation layer irrespective of the area of the isolation layer, a related art has used a technique of forming a dummy active region on the field region. However, the dummy active region may cause noise in a mixed signal integrated circuit which uses both analog and digital signals on a same chip.